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1 for more information www.linear.com/ltc2874 typical a pplica t ion fea t ures descrip t ion quad io-link master hot swap controller and phy the lt c ? 2874 provides a rugged, 4-port io- link power and communications interface to remote devices connected by cables up to 20m in length. output supply voltage and inrush current are ramped up in a controlled manner using external n- channel mosfets, providing improved robustness compared to fully integrated solutions. wake-up pulse generation, line noise suppression, con - nection sensing a nd automatic restart after fault conditions are supported, along with signaling at 4.8kb/s, 38.4kb/s, and 230.4kb/s. configuration and fault reporting are exchanged using a spi-compatible 4- wire interface that operates at clock rates up to 20mhz. the ltc2874 implements an io-link master phy. for io-link device designs, see the lt ? 3669. quad-port 200ma power source and signaling interface a pplica t ions n io-link masters n intelligent sensors and actuators n factory automation networks l, lt , lt c , lt m , linear technology, the linear logo, module are registered trademarks and hot swap is a trademark of linear technology corporation. io-link is a registered trademark of profibus user organization (pno). all other trademarks are the property of their respective owners. n io-link ? compatible (com1/com2/com3) n 8v to 34v operation n hot swap? controller protected supply outputs n discrete power mosfets for ruggedness and flexibility n configurable 100ma (4-port), 200ma (2-port), or 400ma (1-port) cq drive capability n automatic wake-up pulse generation n automatic cable sensing n cq pins protected to 50v n configurable l+ current limit with foldback n short circuit, input uv/ov and thermal protection n optional interrupt and auto-retry after faults n 2.9v to 5.5 v logic supply for flexible digital interface n no damage or latchup to 8kv hbm esd n 38-lead (5mm 7mm) qfn and tssop packages operating waveforms sense + v dd v cc c v l irq irq sense ? 1 sense ? 2 sense ? 3 sense ? 4 txenn txdn rxdn cs sck sdi sdo gate1 gate2 gate3 gate4 l+1 cq1 l+2 cq2 l+3 cq3 l+4 cq4 ltc2874 8v to 34v 2.9v to 5.5v 2874 ta01a gnd gnd 4.7k 1f 0.2 10 4 4 4 100f 1f 4s/div 20v/div load: 4nf cq1, cq3: slew = 0 cq2, cq4: slew = 1 2874 ta01b cq4 cq1 cq2 cq3 3 1 4 3 2 2 2 2 ltc 2874 2874fb 1 4 3 1 4 3 1 4
2 for more information www.linear.com/ltc2874 p in c on f igura t ion a bsolu t e maxi m u m r a t ings input supplies v dd ........................................................ C0. 3 v to 40 v v l ............................................................ C0. 3 v to 6v input voltages cs , sck , sdi , txd .................................. C 0.3 v to 6v tx en ............................................ C 0.3 v to v l + 0.3 v cq ................................................... v dd C 50v to 50 v gat e C l+ ( note 4) ................................ C 0.3 v to 10 v l+ ............................................................. C6 v to 50 v sense + , sense C ...................... v dd C 2v to v dd + 2v (notes 1, 2, 3) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 txen4 gate4 sense ? 4 l+4 cq4 cq3 gate3 sense ? 3 l+3 sense + v dd gate2 sense ? 2 l+2 cq2 cq1 gate1 sense ? 1 l+1 txd4 rxd4 txen3 txd3 rxd3 cs sck sdi gnd gnd v l txen2 txd2 rxd2 sdo irq txen1 txd1 rxd1 39 gnd t jmax = 150c, ja = 25c/w (note 5) exposed pad ( pin 39) is gnd, must be soldered to pcb 13 14 15 16 top view 39 gnd uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1cq4 cq3 gate3 sense ? 3 l+3 sense + v dd gate2 sense ? 2 l+2 cq2 cq1 txd3 rxd3 cs sck sdi gnd gnd v l txen2 txd2 rxd2 sdo l+4 sense ? 4 gate4 txen4 txd4 rxd4 txen3 gate1 sense ? 1 l+1 rxd1 txd1 txen1 irq 23 22 21 20 9 10 11 12 t jmax = 150c, ja = 34c/w (note 5) exposed pad ( pin 39) is gnd, must be soldered to pcb output voltages gat e .......................................... C0. 3 v to (v l+ ) + 15v irq .......................................................... C0. 3 v to 6v rx d , sdo ..................................... C 0.3 v to v l + 0.3 v operating temperature range ltc 287 4 i .............................................. C 40 c to 85 c maximum junction temperature .......................... 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) fe p ackage ....................................................... 30 0 c ltc 2874 2874fb
3 for more information www.linear.com/ltc2874 o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc2874ife#pbf ltc2874ife#trpbf ltc2874fe 38-lead plastic tssop C40c to 85c ltc2874iuhf#pbf ltc2874iuhf#trpbf 2874 38-lead (5mm 7mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units input supply v dd input supply operating range 24vmode = 0 24vmode = 1 l l 8 20 34 34 v v i dd v dd input supply current, all ports enabled drven = 0xf, enl+ = 0xf, illm = 0x0 l 5 8 ma v dd(uvl) uv lockout v dd rising l 5.5 6 6.5 v uv lockout hysteresis 0.13 v v dd(uvth) uv bit threshold v dd rising 24 vmode = 1 24vmode = 0 l l 16.2 6.8 16.8 7.1 17.4 7.4 v v uv bit threshold hysteresis 0.2 v v dd(ovth) ov bit threshold v dd rising, ov_th = 0x1 l 31 32 33 v ov bit threshold hysteresis 0.4 v logic supply v l logic supply range l 2.9 5.5 v i l v l logic supply current digital inputs at 0v or v l l 0.1 1 ma l+ power supply output v l+(pgth) l+ power good threshold v l+(pgth) = v dd C v(l+) l 1.2 1.5 1.9 v l+ power good hysteresis 100 mv v cb(th) circuit breaker threshold v cb(th) = v(sense + ) C v(sense C ) (note 7) v acl C 0.8 mv v acl analog current limit voltage v acl = v(sense + ) C v(sense C ) v(l+) = 0v, fldbk_mode = 1 v(l+) = v dd C 1v start-up, 2xptc enabled, v(l+) > 18v (note 7) l l 9.2 42 16.7 50 100 24.2 58 mv mv mv t oc(l+) l+ pin oc fault filter v(sense + ) C v(sense C ) = 250mv, lptc = 0x03 (figure 1) l 110 122.5 135 s t d(acl) v sense to gate low v(sense + ) C v(sense C ) = 250mv, lptc = 0x03 (figure 1) c g = 0nf c g = 10nf l 19 24 25 s s start -up current pulse duration 2xptc = 0x0 l 52 62 72 ms sense C pin input current v(sense C ) = 24v l 0 10 25 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. unless otherwise noted, v dd = 24v, v l = 3.3v, and registers are reset to their default states. (note 2) ltc 2874 2874fb
4 for more information www.linear.com/ltc2874 symbol parameter conditions min typ max units gate drive v gate external n-channel gate drive (v gate C v l + ) i(gate) = C1a v dd = 17v to 30v v dd = 8v l l 10 4.5 13 15 15 v v i gate(up) gate pin output current, sourcing v(sense + ) C v(sense C ) = 0v, v(gate) = 1v l C10 C14 C20 a i gate(dn) gate pin output current, sinking enl+ = 0, v(gate) = 10v 1.2 ma i gate (lim) pull-down current from gate to source during uvlo or l+ oc timeout event v( sense + ) C v( sense C ) = 0.2v , v gate = 10v 90 ma (v gate C v l+ ) for power good v(l+) = 8v to 30v l 3.0 3.8 4.5 v cq line driver v rqh , v rql residual voltage (note 6) output high, i(cq) = C100ma output low, i(cq) = 100ma l l 1.2 1.1 1.6 1.5 v v i qpkh , i qpkl wake-up request (wurq) current (figure 2) l 500 700 ma i qh , i ql current limit (figure 3) l 110 160 230 ma t oc(cq) overcurrent timeout c l = 100pf, v dd C cq or cq = 5v (figure 3) slew = 0, sio_mode = 0 slew = 1, sio_mode = 0 l l 13 13 24 24 s s cq line receiver v thh input high threshold voltage 24vmode = 1 24vmode = 0 l l 10.5 0.5 ? v dd 11.9 13 0.7 ? v dd v v v thl input low threshold voltage 24vmode = 1 24vmode = 0 l l 8 0.3 ? v dd 9.4 11 0.5 ? v dd v v v hys input hysteresis 24vmode = 1 24vmode = 0 l l 2.0 0.05 ? v dd 2.5 2.9 0.2 ? v dd v v input resistance v(cq) = v dd C 1v, illm = 0x0 l 390 510 630 k v oh output high voltage i(rxd) = C100a l v l C 0.4 v v ol output low voltage i(rxd) = 100a l 0.4 v digital i/o input threshold voltage 2.9v v l 5.5v l 0.33 ? v l 0.67 ? v l v input leakage current 0v v in v l cs, txd sck, sdi, txen l l C10 C1 1 10 a a input capacitance (note 7) l 2.5 pf v oh(sdo) sdo output high voltage i(sdo) = C1ma l v l C 0.4 v v ol(sdo) sdo output low voltage i(sdo) = 1ma l 0.4 v v ol(irq) irq open drain output low voltage i(irq) = 3ma i(irq) = 5ma l l 0.4 0.7 v v other pin functions i ll receive-mode load/discharge current illm = 0x3, 0v v(cq) 5v illm = 0x3, 5v < v(cq) 30v illm = 0x2, 5v < v(cq) 30v illm = 0x1, 5v < v(cq) 30v l l l l 0 5 3.2 2.2 6.2 6.2 3.7 2.5 6.8 6.8 4.2 2.8 ma ma ma ma input to ga te off propagation delay enl+ uvlo_vdd (note 7) or ov_vdd event l l 2 10 4 15 s s e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. unless otherwise noted, v dd = 24v, v l = 3.3v, and registers are reset to their default states. (note 2) ltc 2874 2874fb
5 for more information www.linear.com/ltc2874 s wi t ching c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. unless otherwise noted, v dd = 24v, v l = 3.3v, and registers are reset to their default states. symbol parameter conditions min typ max units gate turn-on delay l 10 20 s t retry auto-retry delay retrytc = 0x5 3.9 s esd protection cq and l+ pins all other pins human body model (note 7) 8 6 kv kv driver and receiver f dtr maximum data transfer rate c l = 4nf slew = 0 slew = 1 l l 38.4 230.4 kb/s kb/s t bit bit time slew = 0 slew = 1 26.04 4.34 s s c cq cq pin input capacitance (note 7) 100 pf driver t dr , t df rise or fall time slew = 0 (figure 4) c l = 100pf c l = 4nf l l 3 3 5.2 5.2 s s slew = 1 (figure 4) c l = 100pf c l = 4nf l l 0.5 0.5 0.869 0.869 s s t phld , t plhd propagation delay c l = 100pf (figure 5) slew = 0 slew = 1 l l 4 1.3 8 3 s s t skewd skew c l = 100pf (figure 5) slew = 0 slew = 1 0.5 0.5 s s t zhd , t zld enable time r l = 10k, c l = 100pf, illm = 0x0 (figure 6) slew = 0 slew = 1 l l 12 3 s s t hzd , t lzd disable time r l = 10k, c l = 100pf, illm = 0x0 (figure 6) l 3 s t wudly wake-up request (wurq) delay (figure 2) l 7.5 20 s t wu wurq pulse duration (figure 2) l 75 80 85 s wurq cooldown t imer l 8.3 10 ms receiver t h , t l detection time (figure 7) t bit = 208.3s (com1), nsf = 0x1 t bit = 26.0s (com2), nsf = 0x2 t bit = 4.34s (com3), nsf = 0x3 l l l 1/16 1/16 1/16 1/10 1/9 1/7 t bit t bit t bit t nd noise suppression time (figure 8, note 9) t bit = 208.3s (com1), nsf = 0x1 t bit = 26.0s (com2), nsf = 0x2 t bit = 4.34s (com3), nsf = 0x3 l l l 1/10 1/9 1/7 1/16 1/16 1/16 t bit t bit t bit t phlr , t plhr receiver propagation delay nsf = 0x0, c l = 100pf (figure 7) l 200 600 ns t skewr receiver skew nsf = 0x0, c l = 100pf (figure 7) 100 ns ltc 2874 2874fb
6 for more information www.linear.com/ltc2874 operation at 230.4kb/s (com3) and 38.4kb/s (com2) driver eye diagram (com3) cq residual voltage vs v dd ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd = 24v, v l = 2.9v to 5.5v unless otherwise noted. (see figure 9) (note 7) symbol parameter conditions min typ max units spi interface t su cs to sck set-up time l 7 ns t hd sck falling to cs hold time l 7 ns t ch sck high time l 19 ns t cl sck low time l 19 ns t ds sdi set-up time l 4 ns t dh sdi hold time l 4 ns t do sck falling to sdo valid c(sdo) = 10pf 4.5v v l 5.5v 2.9v v l < 4.5v l l 20 40 ns ns sck frequency 50% duty cycle (note 8) l 20 mhz note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all voltages are with respect to gnd. all currents into device pins are positive; all currents out of device pins are negative. note 3. numerical subscripts corresponding to port number are sometimes omitted from pin names for brevity. note 4. an internal clamp limits each gate pin to a minimum of 10v above its respective l+ pin. externally driving these pins to voltages beyond the clamp may damage the device. note 5. this ic includes current limiting and overtemperature protection that are intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. overtemperature protection will become active at a junction temperature greater than the rated maximum operating temperature. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 6. residual voltages are defined as follows: v rqh = v dd C v(cq), and v rql = v(cq) C v(gnd). note 7. guaranteed by design and not production tested. note 8. sck frequency is limited by sdo propagation delay as follows: t sck 2 ? (t do + t s ), where t s is the setup time of the receiving device. note 9. guaranteed by production testing of t h and t l . typical p er f or m ance c harac t eris t ics t a = 25c, v dd = 24v, v l = 3.3v, unless otherwise noted. v dd supply voltage (v) 5 residual voltage (v) 1.2 1.3 1.4 25 30 2874 g03 1.1 1.0 10 15 20 35 v rql 85c 25c ?40c i cq = 100ma v rqh 1s/div 10v/div prbs = 2 8 ? 1 cq1: load = 4nf cq4: 20m cable + 1nf + 300 cq2, cq3: asynchronous com3 switching l+1 to l+4: enabled and bypassed at far end 2874 g02 cq1 no cable 20m cable (far end) cq4 10s/div 20v/div load: 4nf cq1, cq3: slew = 0 cq2, cq4: slew = 1 2874 g01 cq1 cq2 cq3 cq4 ltc 2874 2874fb
7 for more information www.linear.com/ltc2874 typical p er f or m ance c harac t eris t ics driver current limit vs temperature cq short circuit protection driver enable/disable driving 20m cable to 1f load driver propagation delay vs temperature cq driver short-circuit current vs short-circuit voltage cq pin current wake-up pulse width vs temperature wake-up current vs temperature 4s/div 10v/div 5v/div 500ma/div txd = gnd sio_mode = 0 load: 50pf 2874 g05 cq short to gnd circuit breaker irq ?i(cq) cq pin voltage (v) ?60 current (ma) 120 160 200 20 40 2874 g09 80 40 0 ?200 ?40 ?80 ?120 ?160 ?40 ?20 0 60 v dd = 30v v dd = 8v before time-out output high output low absmax t a = 25c, v dd = 24v, v l = 3.3v, unless otherwise noted. temperature (c) ?50 pulse width (s) 85.0 50 75 2874 g11 82.5 75.0 80.0 77.5 ?25 0 25 100 i qpkl pulse, v dd = 30v i qpkl pulse, v dd = 20v i qpkh pulse, v dd = 30v i qpkh pulse, v dd = 20v load = 26 to gnd or v dd temperature (c) ?50 current (ma) 1000 50 75 2874 g12 900 400 700 600 800 500 ?25 0 25 100 i qpkl , v dd = 30v i qpkl , v dd = 20v i qpkh , v dd = 30v i qpkh , v dd = 20v load = 26 to gnd or v dd 100s/div 10v/div 5v/div 10v/div nsf = 0x2 slew = 0 sio_mode = 1 2874 g07 cq (near end) cq (far end) rxd (near end) 2s/div 2v/div 10v/div slew = 1, illm = 0x0 load: 100pf (gnd) + 10k (v dd or gnd) 2874 g06 txen cq (txd low) cq (txd high) temperature (c) ?50 delay (s) 4 5 6 50 75 2874 g08 3 2 1 0 ?25 0 25 100 load = 100pf slew = 0 slew = 1 t plhd t phld cq pin voltage (v) ?60 current (a) 100 140 20 40 2874 g10 60 20 ?140 ?20 ?60 ?100 ?40 ?20 0 60 85c ?40c v dd = 8v v dd = 30v v dd ? v(cq) = 50v illm = 0 driver off temperature (c) ?50 current (ma) 600 800 1000 50 75 2874 g04 400 200 0 ?25 0 25 100 four connected cq pins two connected cq pins each cq pin ?i qh i ql ltc 2874 2874fb
8 for more information www.linear.com/ltc2874 l+ start-up with 100f load l+ start-up (set by c g ) and disable 2x current pulse at 18v typical p er f or m ance c harac t eris t ics wake-up pulse: i qpkh wake-up pulse: i qpkl receiver output voltage vs load current receiver input threshold vs temperature receiver propagation or filter delay vs temperature receiver pulse rejection and detection delay vs temperature 20s/div 5v/div 5v/div 10v/div cq load: 4nf + 100 2874 g13 16th sck cq irq 20s/div 5v/div 5v/div 10v/div cq load: 4nf + 100 2874 g14 16th sck cq irq t a = 25c, v dd = 24v, v l = 3.3v, unless otherwise noted. temperature (c) ?50 delay (s) 23 50 75 2874 g17 22 0 20 4 3 2 21 1 ?25 0 25 100 rising rxd falling rxd nsf = 0x1 load = 100pf nsf = 0x2 nsf = 0x3 nsf = 0x0 temperature (c) ?50 pulse width (s) 23 50 75 2874 g18 22 0 20 4 3 2 21 1 ?25 0 25 100 detected rejected nsf = 0x1 v l = 2.9v to 5.5v nsf = 0x2 nsf = 0x3 4ms/div 10v/div 2xptc = 0x1 lptc = 0xb 2874 g19 fldbk_mode = 1 fldbk_mode = 0 l+1 l+2 l+3 l+4 load current (ma) 0.0 voltage (v) 0.5 0.3 2874 g15 0.4 0.0 0.2 0.3 0.1 0.1 0.2 0.4 v l = 2.9v v l = 3.3v v l = 5v v l ? v oh v ol temperature (c) ?50 threshold voltage (v) 13 50 75 2874 g16 12 8 10 11 9 ?25 0 25 100 v dd = 30v v dd = 20v v thh v thl 24vmode = 1 40ms/div 10v/div 2xptc = 0x1 fldbk_mode = 0 load: 10f lptc = 0xd c g : 22nf 2874 g20 l+1 l+2 l+3 l+4 100ms/div 10v/div 200ma/div 2xptc = 0x0 fldbk_mode = 0 load: 3500f 2874 g21 l+ ?(l+) ltc 2874 2874fb
9 for more information www.linear.com/ltc2874 typical p er f or m ance c harac t eris t ics i gate(up) vs temperature external mosfet v gs (?v gate ) vs temperature l+ overcurrent behavior l+ current limit sense voltage vs temperature l+ power good threshold vs temperature logic input threshold vs v l supply voltage v dd overvoltage indicator vs temperature l+ overcurrent circuit breaker delay vs ?v sense duty cycle i ll sinking current vs cq voltage temperature (c) ?50 current (a) ?14.4 50 75 2874 g22 ?13.6 ?14.0 ?13.8 ?14.2 ?25 0 25 100 v dd = 30v v dd = 20v v dd = 8v four ports on temperature (c) ?50 ?v gate (v) 14.0 50 75 2874 g23 12.0 13.0 12.5 13.5 ?25 0 25 100 v dd = 30v v dd = 20v v dd = 8v four ports on t a = 25c, v dd = 24v, v l = 3.3v, unless otherwise noted. temperature (c) ?50 supply voltage (v) 40 50 75 2874 g28 30 34 38 36 32 ?25 0 25 100 v dd = rising ov_th = 0x3 ov_th = 0x2 ov_th = 0x1 temperature (c) ?50 v dd ? l+ (v) 1.8 50 75 2874 g26 1.2 1.5 1.6 1.7 1.4 1.3 ?25 0 25 100 v dd = 30v v dd = 20v v dd = 8v rising l+ falling l+ cq pin voltage (v) 0 current (ma) 8 30 40 2874 g29 0 6 4 2 10 20 50 input resistance illm = 0x3 illm = 0x2 illm = 0x1 illm = 0x0 t a = 85c t a = 25c t a = ?40c v l supply voltage (v) 2.5 threshold voltage (v) 3.0 4.5 5.0 2874 g27a 1.0 2.0 2.5 1.5 3.0 3.5 4.0 5.5 t a = 85c t a = 25c t a = ?40c input low input high duty cycle (%) 0 delay (ms) 10000 80 2874 g27b 0.01 100 10 1 1000 0.1 20 40 60 100 lptc = 0xf lptc = 0x8 lptc = 0x4 lptc = 0x2 lptc = 0x1 lptc = 0x0 100s/div 10v/div 5v/div 500ma/div lptc = 0x4 irqmask = 0xf6 fldbk_mode = 0 load: 50pf 2874 g24 l+ irq load step (8) ?i(l+) circuit breaker temperature (c) ?50 ?v acl (mv) 18.0 50 75 2874 g25 15.0 16.5 17.0 16.0 15.5 17.5 ?25 0 25 100 v dd = 30v v dd = 20v v dd = 8v v(l+) = 0v fldbk_mode = 1 ltc 2874 2874fb
10 for more information www.linear.com/ltc2874 typical p er f or m ance c harac t eris t ics v dd supply current vs supply voltage v dd supply current vs data rate sdo voltage vs load current cq driver edge time vs supply voltage driving 12v relay coils t a = 25c, v dd = 24v, v l = 3.3v, unless otherwise noted. v dd supply voltage (v) 5 supply current (ma) 70 20 25 2874 g30 0 20 10 60 50 40 30 10 15 3530 cq1 to cq4 switching 1010, l+1 to l+4 enabled sio, 0.6kb/s, 1f com2, 0.05nf com2. 4nf com2, 10nf com3, 0.05nf com3, 1nf com3, 4nf date rate (kb/s) 0 supply current (ma) 70 150 200 2874 g31 0 20 10 60 50 40 30 50 100 250 4nf 1nf v dd = 30v v dd = 20v com3 com2 0.05nf com1 cq1 to cq4 switching 1010 l+1 to l+4 enabled load current (ma) 0 voltage (v) 6 3 4 5 6 7 2874 g32 0 2 1 5 4 3 1 2 8 v l = 5v v l = 3.3v v l = 2.9v v dd supply voltage (v) 5 edge time (s) 15 20 25 2874 g33 0 2 1 5 4 3 10 3530 rising falling load = 100pf slew = 1 slew = 0 20ms/div 10v/div 24vmode = 0 slew = 0 sio_mode = 1 relays: g2r-1-e-t130 dc12 + catch diode 2874 g34 cq1 cq2 cq3 cq4 ltc 2874 2874fb
11 for more information www.linear.com/ltc2874 p in func t ions cq2 (pin 15/pin 11): port 2 c/q line. see cq1. cq1 (pin 16 /pin 12): port 1 bidirectional communication or signaling ( c/q) line. when the port 1 driver is enabled ( either by txen1 or under spi control), this pin is an output referenced to gnd, inverted in polarity with respect to the txd1 input. otherwise, this pin is an input that a remote device may drive and an optional, programmable current sink is active. receiver output rxd1 monitors this pin in both cases. gate1 (pin 17/pin 13): gate drive for external n-channel mosfet, port 1. when the mosfet is turned on, a 14a current drives the gate to 13 v above the l+1 output supply voltage. during a current limit condition, the voltage at gate1 reduces to maintain constant l+ port current. if a timer expires, gate1 pulls down, turning off the mosfet, and a toc_l+ event is recorded. sense C 1 (pin 18/pin 14): l+1 supply current sense negative input. an external sense resistor, r s1 (normally 0.2), connected between this pin and sense + programs the load current limit (?v acl /r s1 ). current is controlled by an analog current limit amplifier and timed circuit breaker. see l+ pin power control in the applications infor- mation section. tie to v dd if unused. do not leave open. l+1 (pin 19 /pin 15): port 1 output supply monitor and source connection. connect this pin to the source of the external mosfet for port 1. rxd1 (pin 20/pin 16): port 1 data output from cq1 receiver, referenced to v l . active even when the driver is on. rxd1 polarity is inverted with respect to the line data at the cq1 pin. (fe/uhf) txen4 (pin 1/pin 35): port 4 cq4 driver enable. see txen1. gate4 (pin 2/pin 36): port 4 gate drive. see gate1. sense C 4 (pin 3/pin 37): l+4 supply current sense nega- tive input. see sense C 1. l+4 (pin 4/pin 38): port 4 power supply output. see l+1. cq4 (pin 5/pin 1): port 4 c/q line. see cq1. cq3 (pin 6/pin 2): port 3 c/q line. see cq1. gate3 (pin 7/pin 3): port 3 gate drive. see gate1. sense C 3 (pin 8/pin 4): l+3 supply current sense nega- tive input. see sense C 1. l+3 (pin 9/pin 5): port 3 power supply output. see l+1. sense + (pin 10/pin 6): l+ current sense common positive input. connect external sense resistors rs1 through rs4, normally 0.2, between this pin and each of the sense C pins in a star configuration. see applica- tions information. tie to v dd if unused. do not leave open. v dd (pin 11/pin 7): supply voltage input (8 v to 34v). bypass to gnd with a 1 f ceramic capacitor placed near the pin and at least 100f additional bulk capacitance. gate2 (pin 12/pin 8): port 2 gate drive. see gate1. sense C 2 (pin 13/pin 9): l+2 supply current sense nega- tive input. see sense C 1. l+2 (pin 14/pin 10): port 2 power supply output. see l+1. ltc 2874 2874fb
12 for more information www.linear.com/ltc2874 p in func t ions (fe/uhf) txd1 (pin 21/pin 17): port 1 data input to cq1 driver, referenced to v l . tie to v l if unused. txen1 (pin 22/pin 18): port 1 cq1 driver enable, refer- enced to v l . tie to gnd if unused. irq (pin 23/pin 19) : interrupt output. open drain output that pulls low to alert the host microcontroller when an event occurs, eliminating the need for continuous software polling . disable individual irq events using the irqmask register. irq typically has a pull- up resistor to v l . sdo (pin 24/pin 20): spi interface data output, refer- enced to v l . rxd2 (pin 25/pin 21): port 2 data output from cq2 receiver. see rxd1. txd2 (pin 26/pin 22): port 2 data input to cq2 driver. see txd1. txen2 (pin 27/pin 23): port 2 cq2 driver enable. see txen1. v l (pin 28/pin 24): logic supply (2.9 v to 5.5 v) for the control logic, registers, receiver outputs, driver inputs, and spi interface. bypass to gnd with at least a 0.1f capacitor. gnd (pins 29, 30, exposed pad pin 39/pins 25, 26, ex - posed pad pin 39): device ground. the exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the pcb. solder to the board and tie directly to the ground plane using thermal vias. sdi ( pin 31/pin 27): spi interface data input, referenced to v l . tie to gnd if unused. sck ( pin 32/pin 28): spi interface clock input, referenced to v l . tie to gnd if unused. cs (pin 33/pin 29): spi interface chip select input (ac- tive low), referenced to v l . tie to v l if unused. rxd3 (pin 34/pin 30): port 3 data output from cq3 receiver. see rxd1. txd3 (pin 35/pin 31): port 3 data input to cq3 driver. see txd1. txen3 (pin 36/ pin 32): port 3 cq3 driver enable. see txen1. rxd4 (pin 37/pin 33): port 4 data output from cq4 receiver. see rxd1. txd4 (pin 38/pin 34): port 4 data input to cq4 driver. see txd1. ltc 2874 2874fb
13 for more information www.linear.com/ltc2874 b lock diagra m slew1 drven1 v l cs sck sdi sdo txen1 sense ? 2 gate2 l+2 cq2 sense ? 3 gate3 l+3 cq3 sense ? 4 gate4 l+4 cq4 txen2 txd2 rxd2 txen3 txd3 rxd3 txen4 txd4 rxd4 txd1 rxd1 wkup1 port 2 port 1 port 3 port 4 nsf1 irq c vl 0.1f 4.7k 2.9v to 5.5v 2874 bd sense + 8v to 34v sense ? 1 v dd control and monitoring registers uvlo and supply monitors thermal protection charge pump to gate drivers v dd ? 1.5v enl+1 l+1 cq1 18v wakeup generation driver control driver control fault control foldback 16.7mv to 50mv 2x pulse pwrgd1 gate1 cable sense fault control gate driver spi ov_vdd uv_vdd uvlo_vdd uvlo_vl rcvr filter + ? illm1 gnd c vdd1 1f r s1 0.2 r gate1 10 q1 1 of 4 cables c vdd2 100f ? + ? + ? + ? + acl ltc 2874 2874fb
14 for more information www.linear.com/ltc2874 tes t c ircui t s / ti m ing diagra m s figure 1. l+ pin overcurrent figure 2. wake-up parameters figure 3. cq pin overcurrent figure 4. driver edge rate 2874 f03 t oc(cq) 50% 50% v dd ? cq or cq gnd or v l txd v dd ? 5v or 5v txen v l cq i(cq) irq 0v 0a v ol(irq) v l 5v ?i qh or i ql a + ? 2874 f04 txd cq txen v l c l txd cq 90% 10% 90% 10% 0v v rql v dd ? v rqh v l t df t dr 2874 f01 t d(acl) ?v cb(th) ?v sense irq ?v gate t oc(l + ) 250mv 0v 13v 2v 0v v l v ol(irq) 50% 2874 f02 t wudly 50% sck (16th clock) cs sck txen 0v or v l r l = 52.3 || 51.7 = 26 v dd r l r l cq sdi i(cq) i(cq) t wu 0.5a 0.5a 0.5a v l 0v 0a i qpkh i qpkl 0a 0.5a ltc 2874 2874fb
15 for more information www.linear.com/ltc2874 tes t c ircui t s / ti m ing diagra m s figure 5. driver timing figure 6. driver enable/disable timing figure 7. receiver timing figure 8. receiver noise suppression 2874 f05 txd cq txen v l c l txd cq 0v v rql v dd ? v rqh v l t phld t plhd v thl(min) v thh(max) 50% 50% t skewd = |t plhd ? t plhd | cq rxd c l 2874 f07 v thh(max) noise suppression off noise suppression on v thl(min) 50% 50% 50% 50% cq rxd rxd 0v v oh v ol v ol v oh v dd t phlr t phlr + t h ? t bit t skewr = |t phlr ? t plhr | t plhr + t l ? t bit t plhr 2874 f08 short glitch rejected long glitch detected t nd cq rxd v dd v thh v thl 0v v oh v ol t bit t bit txen cq v l or gnd gnd or v dd c l r l 2874 f06 v thh(max) v thl(min) 50% 50% txen cq cq 0v v dd ? v rqh 0v v dd ? 3v 3v v rql v dd v l t zhd t hzd t zld t lzd ltc 2874 2874fb
16 for more information www.linear.com/ltc2874 tes t c ircui t s / ti m ing diagra m s figure 9. spi interface timing (read) figure 10. spi interface timing (write or wrtupd) 2874 f10 cs sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sdi c1 c2 c0 a3 a2 a1 a0 x d7 d6 d5 d4 d3 d2 d1 d0 sdo hi-z hi-z 2874 f09 cs sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sdi 00 0 a3 a2 a1 a0 x x x x x x x x x sdo d7 d6 d5 d4 d3 d2 d1 d0 t su t ds t dh t ch t hd t cl hi-z t sck hi-z t do ltc 2874 2874fb
17 for more information www.linear.com/ltc2874 o pera t ion the ltc2874 is an industrial master hot swap bus controller and physical interface ( phy) that provides power and communication to four independent 3-wire ports through cables up to 20 m in length ( see figure 11a). the primary applications are 24 v systems specified by iec 61131-9 single-drop communication interface (sdci) for small sensors and actuators, commonly known as io-link. each port on the ltc2874 includes a hot swap power supply output, data transceiver, and a current sink, as shown in figure 11 b. this set of features allows a typical master controller for four ports to be built with the ltc2874, a host microcontroller, and four power mosfets. the basic configuration is shown on page 1. the ltc2874 turns each ports supply voltage on and off in a controlled manner using external n- channel mosfets . external sense resistors individually set the current limits for each port. optional foldback behavior reduces maximum power dissipation in the external mosfets over their operating range. each output is protected by a circuit breaker that responds to an overcurrent fault after a programmable timeout delay. a current- pulse- upon-18v feature provides additional io-link capability for driving heavy, nonlinear loads. the rugged ltc2874 line inter face has been designed to tol- erate abusive conditions encountered on cable interfaces. the cq pins will tolerate 50 v above lC ( gnd) and C50v from v dd . the l + pins offer commensurate ruggedness for power supply outputs ( see absolute maximum ratings). discrete power mosfets offer the best possible system ruggedness and allow design flexibility. they also ensure that ports remain fully independent in the event of extreme fault conditions. normally, the ltc2874 will automatically restart after supply overvoltage or port overcurrent timeout faults. the auto-retry delay is programmable. alternatively, latchoff behavior is available. overcurrent circuit breaker delays for cq pins are mode dependent; for l+ pins they are programmable. the ltc2874 provides a 4- wire spi-compatible interface for configuration and monitoring. the host can detect faults and other events by polling four event registers or by monitoring the irq pin, a programmable interrupt request. standalone operation the ltc2874 is designed for use with a host controller. the spi-compatible interface is the only means of operating the hot swap power supply outputs. the transceivers can operate standalone without the serial interface, restricted by the default register configuration settings. figure 11. (a) sdci class a 3-wire interface (b) ltc2874 master 3-wire interface port the bidirectional cq pins are individually programmable to operate in coded switching ( com) or switching signal (standard io, or sio) format with reconfigurable behavior including slew rate, noise suppression filter, and sinking current. drivers are protected against overcurrent faults by circuit breakers that respond to a fault condition after a mode-specific delay. for io-link compatibility, under spi control, the ltc2874 automatically generates 80s wake-up request (wurq) pulses with correct polarity. l+ c/q l? l+ l? i ll c/q l+, l?: power supply c/q: communication or switching signal (a) (b) 2874 f11 master device hot swap v dd drv ltc 2874 2874fb
18 for more information www.linear.com/ltc2874 drivers the ltc2874 line drivers convert digital levels at the txd pins to inverted polarity line levels at the cq pins. drive at data rates of up to 230.4 kb/s. for io-link operation, they support com1, com2, and com3 transmission. the four drivers operate concurrently and independently. the ltc2874 line drivers are current limited to 160 ma. each is protected by an overcurrent circuit breaker with mode- selectable timeout. for normal signaling (sio_mode = 0), the circuit breaker will trip after being in current limit for 15s. this timeout is more than sufficient to support io- link requirements. the drivers feature a controlled programmable slew rate for optimum emc performance. rise and fall times are programmed using a register bit and are independent of the v dd supply voltage. set each drivers slew bit high for edge times of 0.5s, or low for edge times of 3s. each driver is enabled either by its txen pin or drven register bit. when disabled, drivers are hi-z and the cq pin impedance is dominated by the i ll current sink (unless disabled) and the receiver input resistance. while the line drivers normally operate push-pull, each can also operate in open-drain mode by driving the data signal into its txen pin. for operation with an external pull-up, tie its txd pin high. for an external pull-down, disable that ports current sink (illm = 0) and tie its txd pin low. sio mode up to 1 f of load capacitance can be driven in sio, or standard i/o, mode. set sio_mode = 1 and reduce the edge rate (slew = 0). in sio mode, the overcurrent circuit breaker timeout is extended to 480s. configuring cq outputs for 200ma or 400ma the ltc2874 driving capability can be increased by connecting cq outputs and operating drivers in parallel. figure 36 shows a 2- port configuration that guarantees a minimum cq drive strength of 200 ma, and figure 37 shows a configuration for 400 ma. combine only cq out - puts from a single ltc2874. a pplica t ions i n f or m a t ion receivers the four receivers convert 24 v signals detected at the cq line inputs to inverted-polarity logic levels at the rxd outputs. receiver threshold behavior is selectable, as shown in figure 12. when the 24 vmode bit is set low, the receiver thresholds for all four ports track the input v dd supply. each receiver has an optional digital noise filter that rejects narrow pulses on the cq line. filter delays of 0.6s, 2.8s or 20.3 s are selected using port-specific nsf register bits. setting nsf = 0x0 disables the filter. when the receiver is operated at an io-link compatible data rate ( com3, com2 or com1) and the nsf bits are set accordingly, the filter rejects pulses shorter than 1/16 of the bit time. figure 13 illustrates the rejection and detec - tion bands for a positive noise glitch. except when hi-z at start-up ( see figure 26), receivers are always active. driver and receiver settings appropriate for sio mode and io-link operation are summarized in table 1. table 1. recommended driver and receiver settings operation slew nsf sio_mode sio 0 0x1 1 com1 0 0x1 0 com2 0 0x2 0 com3 1 0x3 0 figure 12. cq receiver input threshold (typical) v dd supply voltage (v) receiver thresholds (v) 10 20 20 24vmode = 1 24vmode = 0 11.9v v thh v thl 0.55*v dd 0.45*v dd 9.4v 15 10 5 0 0 2874 f12 30 40 ltc 2874 2874fb
19 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion current sinks each cq pin has a programmable current sink for use with sensors having high side outputs. each ports current sink is independently set to a value of 0ma, 2.5ma, 3.7 ma, or 6.2ma with port-specific illm register bits. the highest setting guarantees 5 ma for io-link. the second setting guarantees 2.2 ma for compatibility with iec 61131-2 digital inputs. each current sink disables when its driver is enabled or a wake-up request is in progress on that port. automatic wake-up generation the ltc2874 generates an 80 s 500 ma wake-up pulse for the purpose of gaining the attention of a remote io- link device. to initiate wurq generation on a particular port, the respective wkup bit must be set high. acting as a pushbutton, the bit will self-clear once the wurq is underway. the sequence begins by automatically determin - ing the correct polarity for the pulse, first by disabling the driver ( as needed) and sensing the cq line for 5 s. the driver switches on to generate the pulse, then returns to its state prior to the wurq (normally off). the complete sequence is shown in figure 14. although wurqs may be generated with the driver enabled , we recommend the following procedure for best results: 1. disable driver. 2. clear any driver fault by setting toc_cq event bit low. 3. generate wurq by setting wkup bit high. several measures prevent overheating during wurq, when driver power dissipation can be high ( for example, easily 15 w at maximum operating voltage). first, if any overtemperature condition is detected when the wkup bit is first set high, polarity sensing and pulse generation are delayed until the condition clears. second, only one port at a time is allowed a wurq, determined by lowest port number in the event of a simultaneous request. third, upon completion of a wurq, an 8.3 ms cool-down interval is enforced before another wurq can be generated. while a wurq is underway on any port, the wkup bits cannot be set . ( their holding latches can be set high with a write command, and even read out, but when updated by an update or wrtupd command, they will clear and not change the register bits themselves. see the serial interface section for more information.) finally, a thermal shutdown condi - tion will cause the driver to turn off. normal overcurrent cir cuit breaker timers are disabled during wake-up. setting the 24 vmode register bit low disables wake-up generation; the wkup bits have no effect and will not self clear. l+ pin power control external mosfet, sense r summary one function of the ltc2874 is to control delivery of power through cables to four remote devices. on each port it does this by controlling the gate voltage of an external power mosfet based on the current monitored by an external sense resistor and the output voltage at the l+ pin. this circuitry couples the raw v dd input supply to each port through the mosfet in a controlled manner that satisfies the power needs of the connected device while minimizing power dissipation in the mosfet and disturbances on the v dd backplane. figure 13. receiver noise rejection and detection behavior for cq positive glitch figure 14. wake-up sequence 2874 f14 wkup bit wkup bit self-clears sense 5s 8.3ms lockout 80s ready again cq wu event bit 2874 f13 glitch duration glitch high level 0v 1/16 t bit nsf = 0x01, 0x10: n = 3/16 nsf = 0x11: n = 4/16 v thh n ? t bit rejected rejected rejected undefined rejected detected ltc 2874 2874fb
20 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion the current limit of each ltc2874 l+ port is set with a resistor of value v acl /i limit . specified variation in v acl (10%) and tolerance of the resistor must be taken into account. for io-link applications ( which require a guaran - teed minimum of 0.2a), 0.2 sense resistors (r s1 to r s4 ) will set the typical limit 25% above the required minimum. inrush control when the l+ supply of any port is enabled (enl+ = 1), the ltc 2874 ramps up the gate pin of that ports external mosfet in a controlled manner. the gate drivers use a shared charge pump that derives its power from v dd . under normal power-up circumstances, the mosfet gate rises until the port current reaches the current limit, at which point the gate pin is servoed to maintain the cur - rent limit . the ramp rate of the l+ port output voltage is: dv(l + ) dt = i(l + ) c l + = v acl r s ? c l + where c l + is the capacitance on the l+ pin, including sup- ply bypass capacitance of the connected device. during this inrush period, an integrating up/down counter times the duration that the current exceeds the circuit breaker threshold v cb(th) . when output charging is complete, the port current falls and the gate pin resumes rising to fully enhance the mosfet and minimize its on- resistance. the final v gs is nominally 13 v. if the timer expires before the inrush period completes, the port is turned off and a toc_l+ fault is reported. the timer delay is adjustable from 17.5 s to 0.25 s using the lptc register bits. optionally, the l + pin ramp rate can be slowed further using the r g c g network shown in figure 22. for a sufficiently large capacitor, the ramp rate is: dv(l + ) dt = dv(gate) dt = i(gate) c g = 14a c g using a c g of 10 nf will cause l+ to ramp on in about 20ms. l+ current limit the ltc2874 actively controls the mosfet gate drive to keep the port current below v acl /r s . it allows the port current to exceed v cb(th) /r s for a limited time before powering down the port. this duration is timed by an integrating up/down counter for that port whose mini - mum timeout, which is common to all ports, is set in the tmrctrl register (0 xc). if the current drops below the circuit breaker current threshold before the timer expires, the timer counts back down at the same rate. this allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 50%; longer duty cycle overloads will turn the port off. l+ current limit foldback protection during port start-up ( inrush) or when a cable is connected (hot-plugged) to an enabled port, most of the supply voltage is dropped across the mosfet as it begins to supply charging current to the remote device. to protect the mosfet from overheating, the ltc2874 has a cur - rent limit foldback circuit that limits the maximum power dissipated by the external mosfet , thereby increasing its robustness. figure 15 shows how v acl is linearly reduced (folded back) according to the voltage on the l+ pin. the circuit breaker voltage v cb(th) is also folded back and remains no higher than v acl . figure 16 shows typical power-on behavior with foldback. foldback mode may interfere with start-up into some resistive loads. setting the fldbk_mode bit low disables foldback behavior. figure 15. l+ foldback characteristic 2874 f15 50 16.7 1.2 3 7 18 24vmode = 0 24vmode = 1 l+ voltage (v) ?v acl (mv) fldbk_mode = 0 fldbk_mode = 1 ltc 2874 2874fb
21 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion when the l+ pin voltage first reaches 18 v, the l+ port current limit is doubled for a timed interval. the current sense voltage v acl is increased 100%, and the circuit breaker time is disabled until the pulse timer expires. the start-up pulse duration is set using the 2 xptc register bits. the default setting of 62 ms satisfies the required minimum of 50 ms for io-link compatibility. durations of 31ms and 124 ms are also available. set the l+ overcurrent timer ( adjusted with the lptc register bits) to a sufficiently high setting to ensure that the circuit breaker doesnt trip before l+ reaches 18 v. setting 2 xptc to 0 x1 disables the start-up pulse function. l+ power good and power changed power good status is signalled when the l+ pin voltage rises to within v l + ( pgth) of the v dd supply rail and the gate to l+ voltage exceeds 3.8 v, indicating that the mosfet is almost fully enhanced. after a 10 s delay, a pwrchng event indicates that the pwrgd status has changed, as shown in figure 18. once an l+ output is disabled, the pwrgd status bit clears and the pwrchng event bit is static. figure 16. l+ enable behavior with foldback figure 17. l+ current pulse capability figure 18. power good status and power changed event 2874 f16 enl+ bit ov v dd i load gate current limited foldback v dd + 13v i(l+) l+ 2874 f18 l+ 10s 10s clear event v dd ? v (l + pgth) pwrgd status bit pwrchng event bit l+ overcurrent fault when a circuit breaker timeout occurs, the corresponding timeout fault event bit ( toc_l+) is set and the gate pin is pulled down to the l+ pin with a 90 ma current. the remaining ports of the ltc2874 are unaffected, and the enl+ bit remains set. if the retry_l+ bit is set, auto- retry will re-enable the port after a delay; otherwise, the port latches off until the event bit is cleared. figure 24 and figure 25 show example behavior. l+ supply current pulse capability the ltc2874 can optionally double the available current ( to 2 ? v acl /r s ) when an l + output supply is first powered on, accommodating connected devices that require higher current during their own start-up phase. this function may be useful in applications where there is no signaling that its safe to turn on downstream dynamic loads. figure 17 shows simplified behavior when connected to a 100 f load with a 0.2 sense resistor and foldback disabled (fldbk_mode = 0). 2874 f17 l+ port current limit 250ma v dd 18v 500ma actual i(l+) enl+ bit l+ 62ms 2x current pulse capability ltc 2874 2874fb
22 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion gate turn-off when a port is disabled (enl+ = 0), its mosfet is turned off with a 1.2 ma current pulling down the gate pin to gnd. the l+ pin voltage drops as c l + discharges. the ltc2874 is designed to turn off the gate rapidly during certain fault conditions to prevent damage to the mosfet. the fault events that initiate a faster shut down include uvlo of either supply, v dd overvoltage (unless ov_allow = 1), and overcurrent circuit breaker timeout (toc_l+). in these cases the gate pin is discharged to the l+ pin with a 90ma current. cable sensing hot-plugging, or the connection and disconnection of cables to an already enabled port, can cause sparking and reliability problems as connector plating wears off over time. connection sensing mode (csense_mode = 1) mitigates this problem, extending connector lifetime. when a port is enabled with this feature active, the ltc2874 waits until it detects an external connection to its l+ pin before enhancing the external mosfet supplying it. the cable sense function identifies cable connections by measuring capacitive loading. the concept is shown in figure 19. when a given port is enabled, the l+ and gate pins are trickle-charged positive with 200 a, keep- ing v gate close to 0 v. the ltc2874 determines that a cable is connected if either l+ doesnt rise within about 40ms ( because it is loaded) or l+ subsequently pulls low (because a connected cable steals trickle current charge). figure 20 and figure 21 illustrate the behavior. at the maximum operating supply, the timer delay accom - modates typically 100 nf of combined l+ and gate pin loading on the master board without falsely detecting a connection. cable disconnection is not sensed. power good ( pwrgd) status is low during the sense and wait states. figure 19. cable sensing state diagram figure 20. cable sense behavior: connection before enl+ figure 21. cable sense behavior: connection after enl+ 2874 f20 l+en bit csense event bit 40ms i sense irq l+ v dd C 1.5 ? v pg(th) gate on cable connected before enl+ 2874 f21 l+en bit v dd C 1.5 ? v pg(th) csense event bit 40ms i sense cable connected after enl+ irq l+ gate on 2874 f19 l+en = 0 l+en = 0 l+ low l+en = 0 40ms l+ low 40ms l+ high 200a sense gate on gate off wait l+en = 1 ltc 2874 2874fb
23 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion l+ current limit stability for many applications the ltc2874 current limit is stable with a minimum of external components. in figure 22, r gate is required to suppress the tendancy for q1 to de- velop parasitic self-oscillation. a value between 10 and 100 is recommended. the bypass capacitors on the v dd input supply play an essential role as well. in some applications, additional components are needed to improve stability. small mosfets with especially low c gs are less stable, as are larger sense resistors r s . improve stability using the r g c g compensation network in figure 22. for r g , choose a value between 100 ( nor- mally sufficient ) and 1 k; for c g , use between 2 nf and 10nf. do not connect c g directly between the gate pin and ground. board level short-circuit testing is recommended. the worst - case condition for current limit stability occurs when the output is shorted to ground after a normal start-up. the capacitor c g serves a dual purpose, also setting the l+ pin ramp rate described in the inrush control section. mosfet selection careful selection of the power mosfet is critical to system reliability. for io-link compatibility, linear technology recommends fairchild fqt 7n 10, or a similar planar process device in a sot-223 package. larger devices may degrade transient performance of current limiting, while smaller devices are more likely to require external compensation (see l+ current limit stability) and require more care to stay within the rated safe operating area (soa). design example the mosfet is sized to handle power dissipation during inrush when l+ loads are being charged. considering the case of a load capacitor c l + , power dissipation during inrush can be determined based on the principle that: energy in the mosfet = energy in c l + this stored energy is 0.5 ? cv 2 . for example: energy in c l + = 0.5 ? 100f ? (30v) 2 = 0.045j with foldback mode disabled, the time it takes to charge up c l + is: t startup = v dd ? c l + v acl r s = 30v ? 100f 50mv 0.2? = 12ms mosfet power dissipation is: p = energy in c l + t startup = 3.75w in foldback mode, this power is reduced further. for io-link applications, another case to consider is the start-up current pulse ( see l+ supply current pulse capa - bility), in which a heavy nonlinear load could be supplied twice the normal current, or 2 ? v acl /r s , for up to 72ms. again assuming 0.2 sense resistors and no benefit from foldback, average mosfet power dissipation is: p = 30v ? (0v +18v) 2 ? ? ? ? ? ? ? 0.5a = 3.0w the soa ( safe operating area) curves of candidate mosfets must be evaluated to ensure that the heat ca- pacity of the package tolerates the more extreme case, 3w for 72 ms. the soa curves of the fairchild fqt7n10 provide for 350 ma at 30v (>10 w) for 100 ms, satisfying this requirement. figure 22. external components for improving stability and controlling inrush current 2874 f22 sense + ltc2874 gate r gate 10 q1 cable c vdd2 100f sense ? r g c g v dd c vdd1 1f c l + r s 0.2 + ltc 2874 2874fb
24 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion power considerations the ltc2874 has two power supply pins: a logic supply pin (v l ) and the primary supply (v dd ). the v l supply powers the control logic, serial interface and spi registers, and allows the ltc2874 to interface with any logic signal from 2.9 v to 5.5 v. bypass v l to gnd with at least a 0.1f ceramic capacitor. there is no power supply sequencing requirement. bypass capacitance between v dd and gnd is important for reliable operation. if a short circuit occurs at one of the l+ output ports, it can take more than 20 s for the ltc2874 to begin regulating the current. during this time the current is limited only by minimal impedance, so a high current spike can cause a voltage transient on the v dd supply with the possibility that the ltc2874 resets due to a uvlo fault. decouple v dd to ground with at least 100f bulk capacitance and a 1f, 100 v x7r ceramic capacitor placed near the v dd pin to minimize spurious resets. supply monitors the ltc2874 monitors various conditions on its two input power supplies, and alerts the host microcontroller when supply levels move outside of their operating range. event bits record when the logic supply v l has moved below its uvlo threshold or when the main supply v dd has moved below its uvlo threshold, below its mode-dependent uv level, or above its programmable ov level ( see figure 23). figure 23. supply uvlo, uv, and ov monitors 2874 f23 18v 32v 34v 36v ov_th[1:0] 24vmode 0v_vdd event uv_vdd event uvlo_vl event status uvlo_vdd event status 6v v dd ? + ? + ? + 10s 7v 17.5v 10s 10s 2v v l por ? + to provide immunity against supply voltage spikes, the v dd event bits have a 10 s filter time. status bits are live (no-delay) indicators. operating above 30v when operating above 30 v, the v dd threshold at which overvoltage circuits disable the cq and l+ pins must be set higher than the default value (32 v). choose a value of 34v or 36v using the ov_th[1:0] register bits. auto-retry or latchoff fault response when a line output is shorted or the v cb(th) threshold is otherwise exceeded, a timed circuit breaker disables the l+ power supply output or cq driver before overheating can damage the mosfet ( l+) or master ( cq). register bits retry_l+ and retry_cq allow independent fault behavior for l+ and cq pins. set these bits high for auto- retry behavior and low for latchoff. default behavior is auto-retry. when configured for auto-retry behavior, the ltc2874 periodically re- enables the pin to check if the fault condition is still present. see erratum #1. the re - trytc[2:0] register bits adjust the retry timer delay from 0.12 s to 15.7 s to allow for cooling. choose retry ( retr ytc) and over current timer ( lptc) settings in tandem to keep the duty cycle of an l+ fault condition sufficiently low to allow for cooling of the external mosfet. in the case of a cq fault condition, even the fastest retrytc setting limits the duty cycle to <1% to allow for cooling of one or more drivers. when configured for latchoff behavior, the ltc2874 disables the respective l+ or cq pin until the overcur - rent event bit is cleared. in this case, clearing the event register initiates a manual retry. the host is responsible for limiting the duty cycle of the fault condition to avoid overheating the l+ mosfet or cq driver. for example, when using the highest available lptc setting, a manual retry interval of 1 s limits the l+ mosfet duty cycle to 20%. in sio mode, a manual retry interval of 5 ms limits the cq driver duty cycle to 10%. ltc 2874 2874fb
25 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion examples of both responses to an l+ fault are shown in figure 24 and figure 25. spi interface the ltc2874 communicates with the host using a spi-compatible 4- wire interface. figure 9 and figure 10 show typical communication waveforms and timing rela- tionships. interrupts are signaled to the host via the irq pin. when the chip select input cs is set low, it enables the sck input buffer and the sdo output. data at the sdi pin is transferred into the shift register at subsequent rising sck edges. for each 16- bit word, the command bits c2 to c0 are loaded first; then address bits a3 to a0; then a don t- care bit; and finally bits d 7 to d 0, which supply a byte of data ( ordered msb-to-lsb) for some commands. data can be transferred to the ltc2874 only when cs is low. sck may be high or low at the falling edge of cs . keep sck low between commands to ensure timely completion of all commands. commands and their formats are shown in table 2. com - mand c odes n ot shown are reserved and should not be used . table 2. ltc2874 command list and format command detail (first) c2c0 a3a0 bit-8 ( last) d7d0 read read register 000 aaaa x xxxxxxxx write write register (no update) 001 aaaa x dddddddd upda te update all registers 010 xxxx x xxxxxxxx wrtupd write one register and update all 011 aaaa x dddddddd reset reset 111 xxxx x xxxxxxxx the ltc2874 allows the response to v dd supply overvoltage faults to be tailored with similar flexibility. normally, this fault causes the l+ and cq pins of all four ports to be disabled. the retry_ov bit selects between auto-retry and latchoff behavior. if the ov_allow bit is set high, the ltc2874 will tolerate overvoltage conditions, signaling the event but not disabling any functions. auto-retry doesnt clear any event registers, nor does writing any event register bit high disable any function. start-up behavior both external supplies must exceed their undervoltage lockout levels for 10 ms before the cq and l+ outputs are allowed to turn on and before v dd events are reported. dur - ing that settling interval, the rxd pins are hi-z. figure 26 shows typical start-up behavior, assuming the v dd supply is the last to power on. figure 25. latchoff fault behavior (for l+ short) figure 24. auto-retry fault behavior (for l+ short) figure 26. cq or l+ pin start-up behavior 2874 f24 toc l+ event bit l+ t oc(l+) t retry t oc(l+) t retry irq 2874 f25 toc l+ event bit l+ t oc(l+) latchoff t oc(l+) latchoff clear event irq 2874 f26 10ms hi-z v dd(uvl) v dd earliest possible transition of l+ if enabled by enl+ or cq if enabled by txen/drven rxd ltc 2874 2874fb
26 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion spi write, update, and wrtupd commands three of the commands relate to writing data to the reg- isters. the write command transfers data from the shift register to the holding latches of any writable register. the update command transfers data from all holding latches to the spi registers. the wrtupd combines these two commands. for the write and wrtupd commands, data is transferred from the shift register on the 16th falling edge of sck. spi read command the read command transfers a byte of data from the holding latches of a spi register to the serial output pin (sdo). transitions occur on falling clock edges, allowing data to be sampled by the spi master on the rising edges, beginning with the 8 th sck. when cs is low, the sdo pin is low except when a high register bit is being read out. when cs is high, sdo is hi-z. figure 27. example spi commands data written to the internal data holding latches can be verified prior to committing data to the spi registers by reading it before an update command is sent. spi reset command the reset command returns default values to the spi register and clears internal latches . it has no effect on the spi data path itself. this command has sticky behavior, not releasing until a subsequent command ( besides reset) is received. continuous transfer capability commonly for spi communication, cs is asserted low once per command word. the ltc2874 also supports continuous transfer in which multiple command words, each accompanied by 16 sck pulses, are grouped in a sequence (figure 28). this feature is useful for software polling or writing to multiple registers. keep cs low until after the last command word in the group. chip select addressing combine ltc2874 devices to build larger masters by assigning each its own cs and sharing the remaining spi interface wires. see figure 40. spi registers the ltc2874 has 15 registers for configuration and monitoring: seven for control, two for status, four to record events, and two to handle interrupts. register bit assignments are summarized in table 3. when v l is below approximately 2 v, the spi serial port resets to power-on states and registers are set to default values. the reset command similarly sets the registers to default values ( with minor differences listed in the last column of table 3) and resets internal control circuits. figure 28. continuous transfer capability 2874 f28 reset write write write write update 16 sck pulses sdi sck cs 16 sck pulses 16 sck pulses 16 sck pulses 16 sck pulses 16 sck |||||||||||||||| command reset write write write update read 0x8 0x9 0xa 0x1f 0xf0 0x00 0x0 2874 f27 (first) (last) sequence at sdi pin 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 ltc 2874 2874fb
27 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion table 3. spi register table reg name d7 d6 d5 d4 d3 d2 d1 d0 default 0x0 irqreg (read only) ot overtemp event occurred suppl y supply event occurred wu wake-up event occurred toc_l+ l+ oc t imeout event occurred p wrchng l+ power changed event occurred toc_cq cq oc t imeout event occurred csense cable sense event occurred reser ved 0100,0000 (v l - on reset) 0000,0000 (spi reset) 0x1 irqmask ot overtemp irq mask suppl y supply irq mask wu wake-up irq mask toc_l+ l+ oc t imeout irq mask p wrchng l+ power changed irq mask toc_cq cq oc timeout irq mask csense cable sense irq mask reser ved 1111,1110 0x2 event1 ot_ sd overtemp shutdown occurred ot _ w arn overtemp warning occurred reserved uvlo_vl v l uvlo event occurred uvlo _vdd v dd uvlo event occurred uv _vdd v dd uv event occurred ov _vdd v dd ov event occurred reser ved 0001,0000 (v l - on reset) 0000,0000 (spi reset) 0 x3 event2 wu4 wake-up event cq4 occurred wu 3 w ake-up event cq3 occurred wu2 w ake-up event cq2 occurred wu 1 w ake-up event cq1 occurred toc_l+4 l+4 oc t imeout event occurred toc _l+3 l+3 oc t imeout event occurred toc_l+2 l+2 oc t imeout event occurred toc_l+1 l+1 oc t imeout event occurred 0000,0000 0x4 event3 pwrchng4 l+4 power changed event occurred p wrchng3 l+3 power changed event occurred pwrchng2 l+2 power changed event occurred pwrchng 1 l+1 power changed event occurred toc_cq4 cq4 oc t imeout event occurred toc_cq3 cq3 oc t imeout event occurred toc_cq2 cq2 oc t imeout event occurred toc_cq1 cq1 oc t imeout event occurred 0000,0000 0x5 event4 cq_sns4 cq4 sense: 0 = cq high 1 = cq low cq _sns3 cq3 sense: 0 = cq high 1 = cq low cq_sns2 cq2 sense: 0 = cq high 1 = cq low cq_sns1 cq1 sense: 0 = cq high 1 = cq low csense4 l+4 cable sense event occurred csense 3 l+3 cable sense event occurred csense2 l+2 cable sense event occurred csense1 l+1 cable sense event occurred 0000,0000 0x6 status1 (read only) ot over- temperature condition wu _cool wurq or cooldown condition uvlo_vdd v dd uvlo condition ov_vdd v dd over- voltage condition oc_l+4 l+4 over- current condition oc _l+3 l+3 over- current condition oc_l+2 l+2 over- current condition oc_l+1 l+1 over- current condition 0000,0000 0x7 status2 (read only) pwrgd4 l+4 power good pwrgd3 l+3 power good pwrgd2 l+2 power good pwrgd1 l+1 power good oc_cq4 cq4 over- current condition oc _cq3 cq3 over- current condition oc_cq2 cq2 over- current condition oc_cq1 cq1 over- current condition 0000,0000 0x8 mode1 24 vmode enable io-link compatible mode csense_ mode enable cable sense mode 2xptc[1:0] l+ start-up 2x current pulse timer control: 00 = 62ms 01 = disabled 10 = 31ms 11 = 124ms fldbk_ mode enable foldback mode retry _ov enable v dd ov auto-retry retry _l+ enable l + pin auto-retry retry _cq enable cq pin auto-retr y 1000,1111 0x9 mode2 slew4 cq4 edge rate: 0 = slow 1 = fast slew3 cq3 edge rate: 0 = slow 1 = fast slew2 cq2 edge rate: 0 = slow 1 = fast slew1 cq1 edge rate: 0 = slow 1 = fast ov_th[1:0] v dd overvoltage threshold select: 00 = 18 v 01 = 32v 10 = 34v 11 = 36v ov_allow allow v dd overvoltage cq _sns_ mode enable cq sense mode 1111,0100 ltc 2874 2874fb
28 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion table 3. spi register table reg name d7 d6 d5 d4 d3 d2 d1 d0 default 0xa nsf nsf4[1:0] noise suppression filter, port 4: 00 = disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s nsf3[1:0] noise suppression filter, port 3: 00 = disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s nsf2[1:0] noise suppression filter, port 2: 00 = disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s nsf1[1:0] noise suppression filter, port 1: 00 = disabled 01 = 20.3s 10 = 2.8s 11 = 0.6s 1111,1111 0xb illm illm4[1:0] sinking current, port 4: 00 = 500k 01 = 2.5ma 10 = 3.7ma 11 = 6.2ma illm3[1:0] sinking current, port 3: 00 = 500k 01 = 2.5ma 10 = 3.7ma 11 = 6.2ma illm2[1:0] sinking current, port 2: 00 = 500k 01 = 2.5ma 10 = 3.7ma 11 = 6.2ma illm1[1:0] sinking current, port 1: 00 = 500k 01 = 2.5ma 10 = 3.7ma 11 = 6.2ma 1111,1111 0 xc tmrctrl lptc[3:0] l+ overcurrent timer control (ports 1 to 4): 0000 = 15s 1000 = 3.9ms 0001 = 30s 1001 = 7.8ms 0010 = 60s 1010 = 16ms 0011 = 120s 1011 = 30ms 0100 = 0.24ms 1100 = 60ms 0101 = 0.5ms 1101 = 0.12s 0110 = 1.0ms 1110 = 0.25s 0111 = 2.0ms 1111 = 0.25s reser ved retrytc[2:0] auto-retry timer control (ports 1 to 4): 000 = 0.12s 001 = 0.24s 010 = 0.5s 011 = 1.0s 100 = 2.0s 101 = 3.9s 110 = 7.9s 111 = 15.7s 1000, 0101 0 xd ctrl1 wkup4 generate wurq on cq4 wkup 3 generate wurq on cq3 wkup2 generate wurq on cq2 wkup1 generate wurq on cq1 drven4 enable cq4 driver dr ven3 enable cq3 driver drven2 enable cq2 driver drven1 enable cq1 driver 0000,0000 0xe ctrl2 enl+4 enable l+4 power supply enl +3 enable l+3 power supply enl+2 enable l+2 power supply enl+1 enable l+1 power supply sio_ mode 4 cq4 sio mode oc timeout 0 = 15s 1 = 480s sio _ mode 3 cq3 sio mode oc timeout 0 = 15 s 1 = 480s sio _mode2 cq2 sio mode oc t imeout 0 = 15 s 1 = 480s sio _mode1 cq1 sio mode oc t imeout 0 = 15 s 1 = 480s 0000,0000 notes : 1: delays are typical unless other wise noted. 2: underlined settings are default values. 3: gray shading indicates read-only register bits. 4: register 0xd wkup bits are pushbuttons that self-clear. 5: reserved bits may be converted to features in a future release of the product. ltc 2874 2874fb
29 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion table 4. summary of ltc2874 event reporting event event register/ event bits irqreg mask bit behavior note overtemperature shutdown level event1 (0x2) ot_sd 7 thermal recovery temperature has reached shutdown level. l+ and cq pins are disabled until condition clears. overtemperature w arning level event1 (0x2) ot_warn 7 thermal recovery temperature has reached warning level. w ake-up requests (wurq) are blocked. v l supply uvlo event1 (0x2) supply 6 10 ms recover y v l below uvlo threshold for 10s. v dd supply uvlo event1 (0x2) supply 6 10 ms recover y v dd below uvlo threshold for 10s. v dd supply uv event1 (0x2) supply 6 signal event only v dd below uv threshold for 10s. v dd supply ov event1 (0x2) supply 6 latchoff or auto-retr y v dd above ov threshold for 10s. l+ and cq pins are disabled unless ov_allow bit set. wake-up event2 (0x3) wu 5 8.3 ms w ait wake-up request (wurq) has started. additional wurqs are blocked for 8.3ms. l+ overcurrent timeout event2 (0x3) toc_l+ 4 latchoff or auto-retr y duration of l+ current limiting has exceeded programmable timeout. l+ power changed event3 (0x4) p wrchng 3 signal event only l+ power status has changed (10s filter). cq overcurrent timeout event3 (0x4) toc_cq 2 latchoff or auto-retr y duration of current limiting has exceeded mode-dependent timeout. cq sense event4 (0x5) cq_sns n/a cq receiver output (read only) indicates cq level (inverted polarity like rxd) when cq_sns_mode bit set high. doesnt signal irq. cable sense event4 (0x5) csense 1 l+ supply t urns on signals cable or load detected when csense_mode bit set high. ltc 2874 2874fb
30 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion event signaling when an event bit is set, in most cases a bit corresponding to the event type also signals high in the irqreg register (0x0). if the corresponding bit in the irqmask register (0x1) is high, the event causes the irq pin to pull low. the irq signal generates an interrupt to the host micro - controller, eliminating the need for continuous software polling. the irqmask register selects which events can gain the hosts attention at a given time. spi receiver the serial interface monitors the cq line interface pins if the cq_sns_mode bit is set. the polarity of the four cq_sns bits matches the polarity of the rxd pins. these bits are reset low when cq_sns_mode isnt enabled (default). driving light bulbs the cq drivers can safely drive small incandescent light bulbs. use sio mode ( sio_mode = 1) and the fastest auto-retry delay (retry_cq = 1, retrytc = 0 x0). the drivers will pulse on and off while the filament initially draws high current as it heats up. figure 29 shows typi - cal waveforms. driving relays having 100ma drive capability, the cq drivers are capable of energizing the coils of many relays. for some applications requiring higher current, the l+ lines may operate as low data rate outputs. figure 39 shows an example of the l+ pins driving 0.5 a relays, with the cq lines connected as relay sense lines. cq line drivers are disabled by pin-strapping txen1 through txen4 low, and cq pin load currents are disabled by setting illm = 0 x0 for each port. activate any relay by setting its enl+ bit high. the relay sense points are converted to logic levels at the rxd pins. if the cq_sns_mode bit is set high, the sense points may be read from register 0x5 via the serial interface. io-link compatible operation table 5 shows typical register settings for io-link com - patible operation. setting the 24 vmode bit high programs the receivers and l + foldback for 24 v operation per figures 12 and 15. table 5. example settings for io-link compatibility reg value default note 0x8 0x8f y io-link compatibility mode enabled; l+ startup 2x current pulse enabled 0x9 0xf4 y 32v v dd overvoltage threshold 0xa 0xff y 0.5s noise suppression filters 0xb 0xff y 6ma sinking currents 0xc 0x85 y toc_l+ timer not required to be set longer than 62ms startup current pulse applications other than io-link table 6 shows typical spi register settings for operating the ltc2874 in a 12v application. setting the 24 vmode bit low selects v dd -ratioed receiver thresholds (figure 12) and l+ foldback optimized for 12v operation (figure 15). additionally, the wkup register bits are deactivated. table 6. example settings for 12v application reg value default note 0x8 0x5f n io-link compatibility mode disabled; l+ start-up 2x current pulse disabled 0 x9 0xf0 n 18v v dd overvoltage threshold 0xa see note C noise suppression filtering as needed 0xb 0x00 n sinking currents disabled larger light bulbs can be driven if microcode defines a faster driver cooling interval between pulses during bulb ignition. set retry_cq = 0 and clear register 0 x4 to begin each new pulse. because this technique defeats built-in protection against driver self-heating, it must be applied carefully. figure 29. driving an incandescent bulb using sio mode and auto-retry 200ms/div 10v/div 50ma/div 2874 f29 cq cm7387-nd 28v t1 ?(cq) ltc 2874 2874fb
31 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion reverse current protection to isolate the v dd input supply against reverse current from l+ outputs and isolate l+ pins against cable distur- bances on other l+ outputs, use the approach shown in figure? 30. add blocking diodes ( d1-d4) to the mosfet drains rather than sources to maximize the mosfet v gs . when the l+ pins are configured with blocking diodes , 1f master- side l + capacitors ( c 1-c 4) are required to mitigate the increased ringing that can occur in cable-driving ap - plications. use a smaller value (100 nf) for applications requiring cable detection. figure 30 shows the placement of tvs diodes for protect- ing the l+ outputs, while figure 31 shows how to protect the cq pins. mosfet fault detection the l+ supply outputs are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external mosfet to be damaged. a failed mosfet may short from source to drain, which will make the port appear to be on when it should be off. the ltc2874 will disable the port if an overcurrent timeout occurs. a failed mosfet may also short from gate to source. this type of short will prevent the ltc2874 from enhancing the mosfet . the host can detect this condition by the per- manent absence of pwrgd. an open or missing mosfet will similarly not produce pwrgd. normally a damaged mosfet will not affect other ports. however, if it causes the sense resistor r s to fuse open, the sense C pin will exceed its absolute maximum rating, which might damage the ltc2874. this condition is signalled to the host by an oc_l+ status bit that remains high even when the supply output is disabled (enl+ = 0). avoid this situation by performing adequate board-level short circuit testing and using surge-rated sense resistors. high temperature considerations for some applications, the pcb must provide heat sinking to keep the ltc2874 cool. solder the exposed pad on the bottom of the package to ground and tie to large copper layers below using thermal vias. figure 30. reverse protection and tvs diode protection for l+ outputs figure 31. tvs diode protection for cq pins sense + v dd sense ? 1 gate1 gnd l+1 l+2 l+3 l+4 ltc2874 2874 f30 d1 d2 d3 d4 v dd 1f c4 c3 c2 c1 100f gnd v dd v dd *optional to extend cq operating range below ground * cq1 cq2 cq3 cq4 ltc2874 2874 f31 surge and esd protection considerations cable interfaces are subject to significant esd events because long cables can store large reservoirs of charge. the ltc2874 cq and l+ line pins feature protection to 8kv hbm with respect to gnd without latchup or damage during all modes of operation and while unpowered. all the other pins are protected to 6kv hbm. in order to further protect the ltc2874 interface ports against surge and contact/air discharge events based on the iec 61000-4-5 standard, additional external protec - tion is required. sm 6t36a or equivalent tvs clamps are recommended for io-link and most other applications. in 24 v applications in which the input supply tolerance does not exceed 15%, sm6t33a or equivalent clamps are also suitable. ltc 2874 2874fb
32 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion ltc2874 power dissipation can be estimated by consider- ing the contributions of drivers and sinking currents for a given application, along with quiescent power dissipated by internal circuits operating from two supplies. in gen - eral, use the higher case of drive mode and receive mode (sinking current) and ignore the other. calculate driver power dissipation by taking the product of cq residual voltage and load current for each port. here we also factor in worst-case limits and maximum possible dc loading on all ports: pd = 4 ? max((i ll ? v dd ), (i rqh/l ? v rqh/l )) + (v dd ? i dd ) + (v l ? i l ) pd = 4 ? max((6.8ma ? 34v), (0.23a ? 1.6v)) + (34v ? 8ma) + (5.5v ? 1ma) = 1.75w for ja of 34 c/w, the increase in junction temperature compared to ambient is 60c. the thermal shutdown circuit signals an ot_sd event and disables the drivers if the internal die temperature is above about 170 c. the drivers turn back on when the internal die temperature drops approximately 15c. when the internal die temperature is above about 140 c, the ot status bit and ot_warn event bit signal, enabling an informed host to intervene. layout guidelines standard power layout guidelines apply to the ltc2874: place the decoupling caps for the v dd and v l supplies near their respective supply pins, use ground planes, and use wide traces wherever there are significant currents. the main layout challenge involves the arrangement of the current sense resistors, and their connections to the ltc2874. because the sense resistor values are small, layout parasitics can cause significant errors. care is required to achieve specified accuracy. figure 32 illustrates the problem. in example figure 32a, two ports have load currents i 1 and i 2 that connect to v dd through a mutual resistance r m . r m represents the combined resistances of any traces, planes, and vias in the pcb that i 1 and i 2 share. the ltc2874 measures the voltage difference between its sense + and sense C pins to sense the voltage drop across r s1 , but as the example shows, r m introduces errors. the second example (figure 32 b) shows how to minimize errors using good layout. the circuit is rearranged so that r m no longer affects v s , and the sense + connection to the ltc2874 is used as a kelvin sense trace. it is not a perfect kelvin connection because all four ports controlled by the ltc2874 share the same sense trace, and because the current through the trace (i k ) is not zero. however, as the equation in figure 32( b) shows, the remaining error is a small offset term. figure 33 shows two ltc2874 chips controlling eight ports (a through h). the ports are separated into two groups of four; each has its own trace on the top pcb layer that connects to the v dd plane through a via. currents from the u1 sub-circuit are effectively isolated from the u2 subcircuit, reducing the layout problem down to 4-port subsections; this arrangement can be expanded for any number of ports. figure 34 shows an example of good 4- port layout. in this case, each sense resistor consists of two resistors in parallel. the four groups of resistors are arranged to minimize the overlap in their current flows, reducing mu - tual resistance. wide copper paths connect each group of resistors to the vias at the center. the sense + kelvin trace connects to the center of the resis - tor array . the via at the center of the sense resistor array has a matching hole in the v dd plane. this arrangement prevents the mutual resistance of the four large vias from influencing the current measurements and introducing errors. an alternative layout is shown in figure 35. io-link disclaimer linear technology corporation attempts to maintain compatibility with the io-link interface and system speci - fication. lt c is not a member of the io-link consortium as set forth by profibus nutzeroganisation (pno) e.v. ltc 2874 2874fb
33 for more information www.linear.com/ltc2874 figure 32. layout affects current limit accuracy: (a) poor and (b) good layouts sense + v dd i dd +v s rs 1 r m mutual resistance i 1 i 1 + i 2 + i dd sense ? ltc2874 signal scale error crosstalk error (a) (b) 2874 f32 rs 2 i 2 v s = i 1 rs 1 + i 1 r m + i 2 r m sense + v dd i dd +v s rs 1 r m kelvin sense line i k i 1 + i 2 + i dd sense ? ltc2874 signal small offset error r k rs 2 i 1 i 2 v s = i 1 rs 1 ? i k r k a pplica t ions i n f or m a t ion figure 34. good pcb layout example figure 33. layout strategy to reduce mutual resistance kelvin sense trace connects to u1 sense + pin four large vias to v dd plane hole in v dd plane vias to drain pin of the port c mosfet located on the opposite side of the board port d r s pin 1 u1 port c r s port a r s port b r s 2874 f34 sense + v dd v dd copper fill vias vias sense ? 1 sense ? 2 sense ? 3 sense ? 4 ltc2874 ports a through d u1 u2 2874 f33 sense + v dd sense ? 1 sense ? 2 sense ? 3 sense ? 4 ltc2874 ports e through h vias vias v dd copper plane by keeping these copper fills separate, mutual resistance between ports a to d and e to h is eliminated. ltc 2874 2874fb
34 for more information www.linear.com/ltc2874 a pplica t ions i n f or m a t ion a. top layer b. inner layer 2 c. inner layer 3 d. inner layer 4 e. inner layer 5 f. bottom layer figure 35. demo board dc1880a layout showing sense resistors (on bottom layer) and tw o of four mosfets ltc2874 q2 q3 cvdd1 gnd vl vdd rs1 rs4 rs2 d2 d3 rs3 ltc 2874 2874fb
35 for more information www.linear.com/ltc2874 typical a pplica t ions figure 36. 2-port configuration with guaranteed 200ma cq drive capability (and 200ma l+ supply) sense + v dd v cc c v l irq sense ? 2 sense ? 3 sense ? 1 sense ? 4 txen1 txen2 txen3 txen4 txd1 txd2 txd3 txd4 rxd1 rxd4 cs sck sdi sdo l+1 cq1 cq2 l+4 cq3 cq4 gate2 l+2 gate3 l+3 ltc2874 8v to 34v 2.9v to 5.5v 2874 f36 gate1 gate4 gnd gnd 100f 4.7k 1f 1f 0.2 10 port 1 q1 q1, q2: fqt7n10 q2 port 2 ltc 2874 2874fb
36 for more information www.linear.com/ltc2874 typical a pplica t ions figure 37. 1-port configuration with guaranteed 400ma cq drive capability (and 400ma l+ supply) sense + v dd v cc c v l irq sense ? 2 sense ? 3 sense ? 4 sense ? 1 txen1 txen2 txen3 txen4 txd1 txd2 txd3 txd4 rxd1 cs sck sdi sdo l+1 cq1 cq2 cq3 cq4 gate2 gate3 gate4 l+2 l+3 l+4 ltc2874 8v to 34v 2.9v to 5.5v 2874 f37 gate1 gnd gnd 4.7k 1f 0.1 10 q1 q1: fqt7n10 100f 1f ltc 2874 2874fb
37 for more information www.linear.com/ltc2874 typical a pplica t ions figure 38. blocking diodes d1-d4 protect v dd against overvoltage faults on l+ outputs, tvs diodes dz surge-protect cable interface sense + v dd v cc c v l irq sense ? 1 sense ? 2 sense ? 3 sense ? 4 txenn txdn rxdn cs sck sdi sdo gate1 gate2 gate3 gate4 l+1 cq1 l+2 cq2 l+3 cq3 l+4 cq4 ltc2874 8v to 30v 2.9v to 5.5v 2874 f38 gnd d1 to d4: schottky dz: sm6t36a q1 to q4: fqt7n10 c1 to c4: 1f (required when using d1-d4) gnd 1f 4.7k 1f c4 c3 c2 c1 0.2 0.2 0.2 0.2 dz dz dz dz dz dz dz dz d1 d2 d3 d4 10 10 10 10 q1 q2 q3 q4 4 4 4 100f 3 1 4 3 2 2 2 2 ltc 2874 2874fb 1 4 3 1 4 3 1 4
38 for more information www.linear.com/ltc2874 a b a b a b a b sense + v dd v cc c v l irq sense ? 1 sense ? 2 sense ? 3 sense ? 4 txenn txdn rxdn cs sck sdi sdo k1 k2 k3 k4 gate1 gate2 gate3 gate4 l+1 cq1 l+2 cq2 l+3 cq3 l+4 cq4 ltc2874 24v 2.9v to 5.5v 2874 f39 gnd gnd 1f 4.7k 1f 80m 80m 80m 80m 10 q1 q2 q3 q4 d4 4 10 10 10 100f d1 to d4: 1n4004 q1 to q4: fqt7n10 d3 d2 d1 typical a pplica t ions figure 39. spi-operated quad relay driver (with cq relay sense) guaranteeing 0.5a coil current ltc 2874 2874fb
39 for more information www.linear.com/ltc2874 figure 40. n-port master hot swap controller and phy typical a pplica t ions 2874 f40 sck sdi sdo cs irq l+ cq gnd ltc2874 sclk mosi miso ss1 irq1 ss2 irq2 ssn irqn sck sdi sdo cs irq l+ cq gnd ltc2874 sck sdi sdo cs irq l+ cq gnd ltc2874 4 ports 4 ports 4 ports l? l? l? c ? ? ? ltc 2874 2874fb
40 for more information www.linear.com/ltc2874 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.75 (.187) ref fe38 (aa) tssop rev c 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev c) exposed pad variation aa ltc 2874 2874fb
41 for more information www.linear.com/ltc2874 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) ltc 2874 2874fb
42 for more information www.linear.com/ltc2874 e rra t a e rratum #1 description in auto-retry mode, clearing the event register re-enables the faulted pin(s) and resets the entry timer, potentially interfering with duty cycle enforcement. work-arounds (a) use latchoff mode. interrupt service routine must limit duty cycle of faulted pin(s) per guidance given in the auto-retry or latchoff fault response section. (b) use auto-retry mode, clearing faults using an interrupt service time (t is ) thats long compared to the retry time (t is > retrytc ? 1.2). (c) use auto-retry mode, clearing faults using an interrupt service time thats short compared to the retry time (t is < retrytc ? 0.8) while also limiting the maximum duty cycle per (a). ltc 2874 2874fb
43 for more information www.linear.com/ltc2874 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 07/14 lowered mosfet gate resistor increased input supply voltage (max) lowered input low threshold voltage (max) updated cable sense timer delay added operating above 30v applications section changed capacitor values on slave port pins 1, 13, 23, 35, 36, 37, 42 3 4 22 24 42 b 05/15 clarified l+ supply current pulse operation clarified pwrchng event behavior clarified auto-retry and latchoff mode operation added erratum #1 21 21 24, 25 41 ltc 2874 2874fb
44 for more information www.linear.com/ltc2874 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2013 lt 0515 rev b ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2874 r ela t e d p ar t s typical a pplica t ion part number description comments lt3669/lt3669-2 industrial transceivers with integrated step down regulator and ldo compatible with io-link interface and system specification, operates from 7.5v to 40v, integrated 100ma/300ma buck and 150ma ldo ltc2854/ltc2855 3.3v 20mbps rs485 transceivers with integrated switchable termination 3.3v supply, integrated, switchable 120 termination resistor, 25kv esd ltc2859/ltc2861 20mbps rs485 transceivers with integrated switchable termination 5v supply, integrated, switchable 120 termination resistor, 15kv esd ltc2862/ltc2865 60v fault protected 3v to 5.5v rs485/ rs422 transceivers 20mbps, protected from overvoltage line faults to 60v, 15kv esd ltc2870/ltc2871/ ltc2872 rs232/rs485 multiprotocol transceivers with integrated termination 3v to 5.5v supply, automatic selection of termination resistors, duplex control, logic supply pin, up to 26kv esd ltm2881 complete isolated rs485/rs422 module ? transceiver + power 3v or 5v supply, 20mbps, 2500v rms isolation with integrated dc/dc converter, integrated switchable 120 termination resistor, 15kv esd ltm2882 dual isolated rs232 module transceiver + power 3v or 5v supply, 1mbps, 2500v rms isolation with integrated dc/dc converter, 10kv esd complete 24v 3-wire power and com3 rate signaling interface to sensor or actuator (one of four available master ports is shown) bd fb out c cpor sw v out or v ldo rt ilim ldo in ldo fb ldo agnd dio en/uvlo l+ q2 cq1 bst sr sync rst sc1 sc2 wake rxd1 txen1 txd1 txen2 txd2 lt3669 gnd 1f 10.2k 0.1f 10f 38.3k 53.6k v out 4.42k 14k v ldo , i ldo ** 3.3v, 100ma 20 meters **i out(max) , is 100ma and i ldo(max) is 100ma (remaining available i out is: 100ma ? i ldo ) f w = 600khz t rst = 12.5ms v out , i out ** 5v, 100ma 470pf 470pf 4.7f 0.1f 82h 2874 ta02 v dd c v l irq sdi sck cs sdo rxd1 txen1 txd1 q1: fqt7n10 surge protection not shown *additional bypass cap as needed l+1 cq1 gate1 sense ? 1 sense + ltc2874 1/4 gnd 0.1f 2.9v to 5.5v * 4.7k 1f 24v 0.2 q1 100f 10 200ma 100ma 100ma 100ma 2 1 4 3 ltc 2874 2874fb 1 4 2 3 1 4 3 5

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